(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to the etching of passivation layers to expose aluminum bonding pads.
(2) Description of Prior Art
Integrated circuits (ICs) are manufactured by first forming discrete semiconductor devices within the surface of silicon wafers. A multi-level metallurgical interconnection network is then formed over the devices contacting their active elements and wiring them together to create the desired circuits. The wiring layers are formed by first depositing an insulating layer over the discrete devices, patterning and etching contact openings into this layer, and then depositing conductive material into these openings. A conductive layer is then applied over the insulating layer which is then patterned and etched to form wiring interconnections between the device contacts thereby creating a first level of basic circuitry. These circuits are then further interconnected by utilizing additional wiring levels laid out over a additional insulating layers with via pass throughs.
Depending upon the complexity of the overall integrated circuit, one or two levels of patterned polysilicon conductors and two or more levels of metallurgy are required to form the necessary interconnections and to direct the wiring to pads to which the chip's external wiring connections are bonded.
The metal wiring layers, typically of an aluminum alloy containing copper and silicon, are deposited by sputtering or vacuum evaporation. An anti-reflective coating (ARC) is deposited over the metal layer in order to reduce light reflection from the metal surface during the subsequent photolithographic exposure of the patterning photoresist. These reflections degrade the image sharpness. Typically the ARC layer consists of about 300 Angstroms of sputter deposited TiN.
After the metal is patterned using reactive-ion-etching (RIE) an insulative layer, typically a borophosphosilicate glass, is deposited and via openings are etch through this layer to provide accesses of the next metal wiring layer to the one below. The TiN also serves as an etch stop during via etching of this insulative layer. The final metallization layer includes the bonding pads which are typically located in the periphery of the integrated circuit. Again, an ARC layer is provided. After the final metallization layer is patterned a passivation layer is applied. This layer seals the device structures on the wafer from contaminants and moisture, and also serves as a scratch protection layer. The passivation layer typically consists of a layer of silicon nitride or phosphosilicate glass (PSG) over a layer of silicon oxide. Both of these layers are deposited by plasma enhanced chemical vapor deposition (PECVD). The passivation layer is then coated with photoresist and openings to the bonding pads are formed by plasma etching.
Referring to FIG. 1, there is shown a cross section of a wafer 10 having semiconductor devices and a multilevel wiring structure represented by the layer 12. An aluminum alloy bonding pad 16 resides atop the uppermost inter metal dielectric (ILD) layer 14. The pad 16 was patterned by a previous photolithographic step wherein the ARC layer 18 was used beneath a photoresist layer. The passivation layer 20, typically silicon nitride or a phosphosilicate glass (PSG), sometimes with a subjacent silicon oxide layer forms a protective coating over the integrated circuit. A layer of photoresist 24 is applied and patterned to provide an access opening 26 to the bonding pad 16 so that the pad may be wire bonded to the external chip package.
In a conventional process the passivation layer is etched by plasma etching using well known fluorocarbon etchants such as CHF.sub.3 and CF.sub.4 and a carrier gas such as He. Endpoint is determined by well known methods such as optical emission spectroscopy wherein the components of the etching plasma are observed over time. When endpoint is observed an over etch period is applied in order to assure complete exposure of the bonding pad. In specific instances, other openings such as access openings to polysilicon fuses, must also be during this etch step. This requires a considerable over-etch of the bonding pad opening because additional layers of dielectric must be penetrated to access the polysilicon fuses. The TiN ARC layer 18 has a high resistance to the fluorocarbon etchants and thus permits a considerable amount of over-etch without penetration of the aluminum bonding pad 16.
After the oxide over-etch period, the gas mixture is changed to etch away the TiN ARC layer 18 in the opening 26, thereby exposing the aluminum bonding pad 16. A preferred etchant for this purpose is sulphur hexafluoride (SF.sub.6) in combination with a fluorocarbon.
A problem with commercially available SF.sub.6, even in high purity dispensings, is that it often contains trace quantities of chlorine. Residual gas analysis has revealed chlorine content of the order of 10 nanograms per gram of SF.sub.6. In some instances levels as high as 2600 nanograms per gram were found.
Referring to FIG. 2 there is shown a cross section of the region of FIG. 1 after the passivation layer 20 and the ARC layer 18 have been etched. These trace amounts of chlorine when combined with moisture have a corrosive effect upon the aluminum surface. Chlorine reacts with the aluminum to form non-volatile AlCl.sub.3 residues 28 which remain on the surface of the exposed bonding pad 16 after the RIE. These residues 28 are extremely hygroscopic and, if allowed to remain exposed on the wafer, react with the slightest moisture to produce acids which cause severe corrosion of the aluminum bonding pad. Free chlorine, entrapped within such residues, is also hydrolyzed by moisture and becomes corrosive to aluminum. A brief discussion of this metal corrosion problem is given by Wolf, S. and Tauber, R. N., "Silicon Processing for the VLSI Era", Vol. 1, Lattice Press, Sunset Beach, Calif., (1986), p563.
In the conventional method the wafer is removed from the RIE tool after the TiN etch, thereby bringing the freshly exposed aluminum surfaces in contact with atmospheric moisture. If chlorine containing residues are present, aluminum corrosion effects become evident within minutes of exposure.
Man, et.al., U.S. Pat. No. 5,533,635 cites a process for stabilizing chlorine containing residues after aluminum metal patterning with chlorine containing etchants by baking the wafer in an atmosphere containing O.sub.2 and CF.sub.4 for between about 5 and 60 seconds. During this baking period residual chlorine is converted to a stable polymer. The polymer and residual photoresist are subsequently removed by ashing and rinsing in DI water.
Mihara et.al. U.S. Pat. No. 5,447,598 shows a method for forming a polymer layer on the sidewalls of a multi-level resist layer but does not address the problem of stabilizing chlorine species with a polymer over an aluminum surface.
Kadomura, U.S. Pat. No. 5,540,812 shows a method for etching aluminum which prevents corrosion by using S.sub.2 F.sub.2 to etch through a subjacent TiW barrier layer. The S.sub.2 F.sub.2 produces a sulfur based sidewall protection film over TiW while causing a fluorine-for-chlorine exchange in a carbonaceous polymer sidewall film which had previously been formed during the aluminum etching with a chlorine based etchant. The sulfur and carbonaceous films are subsequently removed by ashing.